In recent years, there has been an increasing opportunity to display plural input video signals simultaneously on a screen of a television receiver, and digital signal processing techniques have been employed when displaying the video signals. Further, as semiconductor processes have become more specific, large-scale circuits have been incorporated in semiconductor integrated circuits.
FIG. 7 is a block diagram illustrating a conventional television receiver having a function of displaying a sub-screen in a main screen, which is disclosed in Japanese Published Patent Application No. Hei.7-115600. Hereinafter, the construction and operation of the conventional television receiver will be described with reference to FIG. 7.
A main tuner 701 and a sub-tuner 702 selectively receive predetermined broadcast waves from among broadcast waves received by an antenna 725. A main-screen composite video signal S701 corresponding to the broadcast wave selected by the main tuner 701 is separated into a luminance signal S703 and a chrominance signal S704 by a YC separation circuit 703. The chrominance signal S704 is inputted to a chrominance demodulation circuit 704, and demodulated into a U signal S705 and a V signal S706 that are color-difference signals. The luminance signal S703, U signal S705, and V signal S706 are inputted to an RGB matrix circuit 706, thereby generating an R signal S707, a G signal S708, and a B signal S709 for the main screen. A synchronous separation circuit 705 separates horizontal and vertical sync signals from the main-screen composite video signal S701, and generates a reference pulse S710 of a horizontal/vertical cycle. The horizontal/vertical cycle reference pulse S710 is inputted to a two-screen control circuit 707, thereby generating a main/sub switching signal S711 that can control switches 721, 722, and 723 for selecting either a main-screen image or a sub-screen image.
On the other hand, a sub-screen composite video signal S702 corresponding to the broadcast wave selected by the sub-tuner 702 is separated into a luminance signal S712 and a chrominance signal S713 by a YC separation circuit 708. The analog luminance signal S712 is converted into a digital luminance signal S714 by an analog-to-digital converter (hereinafter referred to as “A/D converter”) 710, and vertical and horizontal bands of the digital luminance signal S714 are removed by a low-pass filter 712 to avoid an occurrence of aliasing in a compression process, and thereafter, a luminance signal S716 obtained from the low-pass filter 712 is written in a memory 714. Likewise, the analog chrominance signal S713 is converted into a digital chrominance signal S715 by an A/D converter 711, and vertical and horizontal bands thereof are removed by a low-pass filter 713, and thereafter, a chrominance signal S717 outputted from the low-pass filter 713 is written in a memory 715. A synchronous separation circuit 709 separates horizontal and vertical sync signals from the main-screen composite video signal S702, and generates a reference pulse S727 of a horizontal/vertical cycle. A memory control circuit 720 controls the writing operation into the memory 715 on the basis of the reference pulse S727, and controls the reading operation from the memory 715 on the basis of the reference pulse S710. The digital luminance signal S718 read from the memory 714 is converted into an analog luminance signal S720 by a digital-to-analog converter (hereinafter referred to as “D/A converter”) 716. The digital chrominance signal S719 read from the memory 715 is converted into an analog chrominance signal S721 by a D/A converter 717, and the analog chrominance signal S721 is demodulated to a U signal S722 and a V signal S723 as color-difference signals by a chrominance demodulation circuit 718. The luminance signal S720, U signal S722, and V signal S723 are inputted to an RGB matrix circuit 719, wherein an R signal S724, a G signal S725, and a B signal S726 for the sub-screen are generated. Either the R signal S707, G signal S708, and B signal S709 for the main screen, or the R signal S724, G signal S725, and B signal S726 for the sub-screen are selected by the main/sub switching signal S711 so that the sub-screen is displayed in a predetermined area of the main screen, and consequently, a composite R signal S729, a composite G signal S730, and a composite B signal S731 are outputted to a monitor 724.
However, the conventional television receiver requires, for the main screen, the YC separation circuit 703, the synchronous separation circuit 705, the chrominance demodulation circuit 704, and the matrix circuit 706, which circuits perform analog processing, and further, it requires, for the sub-screen, the YC separation circuit 708, the synchronous separation circuit 709, the chrominance demodulation circuit 718, and the matrix circuit 719, which circuits perform analog processing, as well as the filters 712 and 713 and the memories 714 and 715 as semiconductor components for digital processing. Thus, the conventional television receiver requires many semiconductor components for signal processing, whereby the number of peripheral circuits also increases, resulting in an increased circuit scale.
Furthermore, since the conventional television receiver employs a lot of analog processing circuits whose characteristics such as temperature characteristics easily vary, the characteristics of the whole products easily vary, and it is difficult to adjust the variations in manufacture factories.
Furthermore, it might be desirable, for commercialization, that the signal processing circuit for the main screen is constituted as a versatile circuit that is independent of the signal processing circuit for the sub-screen and is also applicable to a television receiver which inserts no sub-screen in the main-screen. However, when the signal processing circuit for the main screen and the signal processing circuit for the sub-screen are fabricated as independent integrated circuits, even if these integrated circuits have sharable components, it is difficult to constitute the both circuits so as to share the components. As a result, it is difficult to reduce the circuit scale of the whole video signal processing apparatus by sharing the components.